GATE CSE 2008
Q31.
The use of multiple register windows with overlap causes a reduction in the number of memory accesses for I. Function locals and parameters II. Register saves and restores III. Instruction fetchesQ32.
In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed isQ33.
Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor? I. It must be a trap instruction II. It must be a privileged instruction III. An exception cannot be allowed to occur during execution of an RFE instructionQ34.
An LALR(1) parser for a grammar G can have shift-reduce (S-R) conflicts if and only ifQ36.
Which of the following describes a handle (as applicable to LR-parsing) appropriately?Q37.
Delayed branching can help in the handling of control hazards The following code is to run on a pipelined processor with one branch delay slot: I1: ADD \leftarrowR2 R7 +R8 I2 : SUB R4 \leftarrowR5 - R6 I3: ADD R1 \leftarrow R2 + R3 I4 : STORE Memory [R4] \leftarrow R1 BRANCH to Label if R1==0 Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any other program modification?Q38.
Delayed branching can help in the handling of control hazards For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or falseQ39.
The Newton-Raphson iteration x_{n+1}=\frac{1}{2}(x_{n}+\frac{R}{x_{n}}) can be used to compute theQ40.
Which of the following are NOT true in a pipelined processor? I. Bypassing can handle all RAW hazards II. Register renaming can eliminate all register carried WAR hazards III. Control hazard penalties can be eliminated by dynamic branch prediction